12
9151AINDCO07/09
ATA8742
8. Application
For the supply-voltage blocking capacitor C
3
, a value of 68 nF/X7R is recommended. C
1
and C
2
are used to match the loop antenna to the power amplifier, where C
1
typically is 8.2 pF/NP0 and
C
2
is 6 pF/NP0 (10 pF + 15 pF in series); for C
2
two capacitors in series should be used to
achieve a better tolerance value and to have the possibility of realizing the Z
Load,opt
by using
standard valued capacitors.
Together with the pins and the PCB board wires C
1
forms a series resonance loop that sup-
presses the 1
st
harmonic, hence the position of C
1
on the PCB is important. Normally the best
suppression is achieved when C
1
is placed as close as possible to the pins ANT1 and ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop
antenna is too high.
L
1
(50 nH to 100 nH) can be printed on PCB. C
4
should be selected that the XTO runs on the
load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF
load-capacitance crystal.
Figure 8-1. ESD Protection Circuit
CLK
VS
PA_ENABLE
XTAL
ANT2
ENABLE
ANT1
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